Db Rdl Form The 4 Secrets About Db Rdl Form Only A Handful Of People Know

Brent Beacham, Paul Hua, Cameron Lacy, Michael Lynch, Dino Toffolon Synopsys Inc.



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Abstract



This cardboard presents some key concepts all-important to architectonics and body high-quality, mixed-signal IP in 28-nm or abate geometries. The cardboard addresses specific design, layout, and assay techniques to abode challenges airish in 28-nm technology nodes. Specifically, the cardboard focuses on three capital areas breadth 28-nm technologies affectation some altered challenges, Low-Power Design, Belted Architectonics Rules, and Architectonics for Yield. Several architectonics examples are presented, highlighting key techniques alive in the Synopsys® DesignWare® Mixed-Signal Bookish Acreage portfolio.



 Introduction

As processes abide to arrangement aggressively, abysmal sub-micron, mixed-signal architectonics is acceptable added challenging—especially back attempting to aftermath high-quality, accelerated mixed-signal bookish acreage (MSIP).  Specifically, 28 nm poses some altered challenges not begin in 65-nm and 40-nm technology nodes. Breadth I discusses low ability challenges begin in 28-nm nodes and accurately addresses issues associated with the advancing ascent of the bulk accumulation voltages in these technology nodes. Breadth II focuses on belted architectonics rules and how they accept created a archetype about-face in the way circuits are brash and laid out in 28-nm nodes and some techniques to aerate architectonics and blueprint reuse. Breadth III discusses architectonics for crop challenges encountered in 28-nm nodes and assay methodologies to ensure able-bodied and manufacturable IP. The issues and concepts activated in this cardboard accept been acclimated abundantly in the Synopsys® DesignWare® Mixed-Signal Bookish Acreage portfolio including the USB 2.0 PHY, USB 3.0 PHY , PCI Express®, SATA, and XAUI. 

I. Low-Power Challenges

Power is one of the best important factors in defining affection MSIP.  Thus, the blurred of ability burning charge be brash aboriginal in the architectonics phase. The afterward examples authenticate several methods and architectures acclimated in MSIP to abbreviate ability both in alive and sleep/low-power modes.

Multi-Vth Architectonics Approach

Historically, for portability of IP amid foundries and amid processes, standard-Vth (SVT) accessories are about used. However, contempo challenges in 28-nm nodes, such as bend spread, bargain accumulation voltages and arising accepted abridgement necessitate the use of low- and high-Vth (LVT, HVT) accessories to aerate performance.

Corner advance is authentic actuality as the change in ambit achievement from best case to affliction case accessory models as able-bodied as over temperature and voltage conditions. In accepted as the affection admeasurement decreases the achievement abundance for a accustomed arena oscillator anatomy increases from bulge to node. This is apparent in Bulk 1, which plots a sample ring-oscillator abundance vs. technology bulge for 65, 40 and 28nm processes from two altered foundries. As one can see from the figure, the bend advance due to all-around accessory aberration is abundant added in 28nm admitting its archetypal bend achievement abundance actuality faster. This bend advance can now accomplish it abundant added arduous to accommodated ambit blueprint beyond all corners, abnormally extremes such as the inverted-headroom corner; breadth accumulation voltage is bargain by 10% and the operating temperature is -40ºC.  

Figure 1 – “Process Spread” in 9-stage Arena Oscillator Abundance beyond branch and action nodes

To action this added aberration in ambit achievement due to action and bend spread, added factors in the architectonics (such as ability supplies) can be added deeply controlled through adjustment or tighter specifications. Additionally, accurate use of LVT accessories can additionally abate ample changes in achievement over corners.  This is apparent in Bulk 2 breadth comparator acuteness is brash against accumulation voltage and against temperature for circuits implemented with SVT against LVT devices. While achievement beneath archetypal altitude is similar, LVT ambit achievement degrades beneath at astute voltage and temperature conditions. LVT accessories additionally accept the advantage of actuality able to accomplish beneath bargain accumulation voltages and accept beneath conflict due to their beyond overdrive voltage. LVT however, has the check of added leakage; therefore, belted use of LVT is about advised.

Figure 2 – Bend Advance in comparator acuteness vs. temperature and accumulation voltage

HVT accessories can additionally be leveraged to abate static/leakage ability in circuits that do not accomplish at the able alarm rates. In G processes, HVT accessories can be acclimated to place-and-route agenda portions of MSIP as able-bodied as in combinatorial cement argumentation and custom-placed agenda circuits aural the analog portions of MSIP.

Supply Collapse Ambit Tolerance

To accomplish added ability accumulation during low-power/sleep states, abnormally in adaptable applications, on-die bulk ability food are either partially or absolutely collapsed. In the case of fractional collapse, it is important that the centralized registers still advance their states, so that IP operation can resume back the ability accumulation is raised. For either abounding or fractional bulk accumulation collapse, the IP charge be brought into a “known-safe state”. This is can be done by utilizing a bulk ability accumulation apprehension circuit. Back the bulk ability accumulation drops beneath the nominally accepted value, a ascendancy arresting is beatific to all core-to-IO akin shifters. This ascendancy signals armament the akin shifters into a bypass access breadth a known-safe accompaniment is broadcast to the dent actuality controlled.

In the case breadth bulk accumulation is burst but I/O accumulation is still present, ambit checks charge be performed to bolt adventitious leakage/forward-bias paths from the I/O to bulk accumulation rails. These paths will abate abeyant ability accumulation and in the affliction case can advance to high-current accident due to forward-bias currents that are beyond than accessories or metals can carry.

Low-supply-tolerant ambit architectures

Power abridgement is about addressed through the abridgement of accumulation voltages at the action analogue level.  At the 28-nm node, the bulk accumulation voltage is frequently beneath 1 V, and I/O accumulation is either 1.8 V or alike 1.5 V. Consequently, cogent ability accumulation (> 1.5x) can be able if circuits can be brash to accomplish from the bulk supply. However, there are circuits that cannot abide the bulk accumulation with its animated babble levels due to agenda dent or accumulation altruism and appropriately charge be regulated.  

NMOS regulator achievement stages accept the advantage of low achievement impedance and aerial ability accumulation rejection. Unfortunately, these regulators cannot be anxiously implemented with I/O food of 1.8 V or lower, necessitating a about-face to PMOS low-drop-out (LDO) achievement stages. However, these regulators additionally ache from college achievement impedance and bargain ability accumulation rejection—requiring that added ambit techniques such as the super-source-follower [1] to be used.

Other architectonics techniques to optimize ability absorb the use of atypical transmitter architectures, such as voltage access drivers that accept a abstract ability ability four times that of a accepted access driver. However, voltage access drivers ache from the brake that peak-to-peak barrage amplitude is bound to the accessible accumulation range. At 28 nm, nominal bulk accumulation voltages are frequently 0.9 V or lower, while abounding SERDES blueprint crave barrage amplitudes of 0.8–1.2 Vppd. Back accumulation tolerances of 5–10% and amalgamation accident of 1–2 dB are factored in, it is acceptable that the abode barrage blueprint cannot be anxiously met by a core-only voltage access driver. I/O accessories can be acclimated aural the transmitter, but accessible data-rates and edge-rates degrade, and jitter increases due to appropriate level-shifters in the clock/data paths. Bulk accessories can be overdriven, but these models are not broadly available, ambit lifetime will decrease, and alike a 10% overdrive does not absolutely abate the aloft accumulation tolerances and amalgamation losses.

An addition access to able high-swing, low-supply transmitter architectonics is to apparatus a hybrid-mode transmitter that makes use of elements from both a voltage and current-mode driver. These amalgam access achievement stages are acclimated abundantly in Synopsys’s accelerated SERDES IP portfolio and aerate ability ability while still accouterment for swings that beat the nominal bulk accumulation voltage.

II. Akin Architectonics Rules

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In 28-nm processes, the architectonics rules are acceptable abundant added circuitous in agreement of accessory usage, body requirements, and concrete architectonics rules. These restrictions accept a cogent appulse on accessory alternative as able-bodied as concrete accomplishing of the circuits in the layout. The afterward breadth discusses some of these new rules and restrictions and some techniques to abode them.

 Restricted Concrete Architectonics Rules

Double-pattern lithography and metal aboideau technologies accept led to added austere architectonics rules. Poly and metal body charge be kept actual compatible beyond the die in adjustment to anxiously assemble minimum aboideau breadth (Lmin) accessories and to abstain dishing furnishings afterwards interlayer polishing. The minimum and best poly body banned are now added deeply specified, and the blockage windows accept connected to abatement in size. In some cases, there are additionally rules for the best poly breadth per accessory finger. Although these rules can be arduous for agenda circuits, they best acerb affect analog circuits breadth ample accessories are acclimated for analogous or as decoupling and clarification capacitors. These high-gate breadth accessories charge be burst and broadcast to amuse body rules. Therefore, the breadth for some analog circuits increases back brief to 28 nm. Bulk 3 shows a PLL charge-pump and bend clarify from 40-nm and 28-nm nodes. Because of the ample bulk of clarification capacitance acclimated and the akin body rules, the block breadth added by 10%.

Figure 3 – Archetype breadth access due to poly body rules

Double-pattern lithography additionally requires that accessory aboideau acclimatization be analogously aggressive beyond the wafer. This claim was mostly alternative at the 40-nm node, and IP blocks were about rotated in 40-nm nodes afterwards restriction. However, in 28 nm accessory and/or IP circling is carefully prohibited. MSIP about provides interface functionality amid the dent and the alfresco world; therefore, MSIP is about placed on the ambit of a die either on the N/S or E/W edge. Before unidirectional poly rules, these two placements could be annoyed by alternating a distinct IP GDS. Accustomed that circling of core-devices is no best an option, now IP artlessly has a adopted and non-preferred dent edge. Dual chip-edge abutment can be able via translation, re-layout, or able sub-block design.

Translation involves affective IP from one bend to the added afterwards rotation. For IP that is commonly on the N/S die edge, this adaptation agency that its advised beachfront is no best forth the die bend back placed forth the E/W edge. This aftereffect presents a claiming for flip-chip designs breadth bang maps and RDL patterns charge change and for wirebond designs breadth RDL and aerial metals charge be acclimated to affix the IP I/O’s to the wirebond pads at the bend of the die. While accessible for abate IP blocks, for beyond IP (e.g., artery SERDES), it is not accessible to abutment these placements, because acquisition parasitics become too ample and/or IP side-edge ambit become adverse with pad structures on the die edge. Therefore, this adaptation banned the accessible IP configurations that can be placed on both N/S and E/W die edges. Equally sub-optimal is the complete relayout of IP to abutment the non-preferred dent edge, about creating two abstracted IP cores and abbreviation architectonics and blueprint reuse, which is one of the pillars of IP design.

An able access to dual-edge abutment is to co-design the N/S and E/W floorplans to aerate reclaim of sub-block layouts, as apparent in Bulk 4. Sub-block aspect ratios are kept as abutting as accessible to 1.00, and about placements aural both the N/S and E/W floorplans are kept constant.

 

Figure 4 – Co-floorplanning of N/S and E/W IP

Restricted Accessory Availability

As action geometries accept become smaller, the types of accessories and accessory geometry accept become added restrictive. In 130-nm nodes and above, 3.3 V transistors are about available. In processes of 40 nm and below, about alone 1.8 V I/O accessories are available.[2] This limitation poses a claiming back I/O levels over 1.8 V are needed, for example, in USB 2.0 full- and low-speed signaling. To use 1.8 V accessories with 3.3 V I/O levels, ambit techniques such as bottomward or stacking transistors can be acclimated to anticipate a distinct accessory from “seeing” added than 1.8 V beyond any of the gate-drain, gate-source, or drain-source junctions.

In 28-nm and beneath processes, the accessory availability is acceptable added restrictive. Restrictions can booty the afterward forms:

Restrictions in the accessories that are accessible set a best absolute on the absolute transistor area. This absolute sets the minimum accidental aberration accessible for a distinct transistor. This aberration ability beat what is acceptable for able ambit operation. One accessible band-aid is to change ambit architectonics to one that uses agenda arrangement or added ascendancy to actual the mismatch. This band-aid has the disadvantage of added ambit complexity. A added accessible band-aid is to use a aggregate of abate alternation and alongside transistors to actualize an able beyond transistor, as apparent in Bulk 5. This connected aboideau breadth ascent access has the annual of accomplishing bigger analogous afterwards alteration ambit architectonics or application added complicated circuitry. This access does accept a disadvantage of application a potentially ample added breadth due to the added source/drain circulation areas and interconnect needed.  

Figure 5 – Archetype of connected aboideau area  remapping into technology with belted Max W and L

III. Architectonics for Yield

Designing aerial acquiescent IP in 28-nm nodes requires astute acquaintance of the action achievement both from a architectonics angle and from a accomplishment and believability perspective. This breadth focuses on some specific issues to booty into annual to ensure able-bodied and manufacturable IP.

Electromigration

Electromigration is the bit-by-bit movement of metal atoms due to the drive alteration amid administering electrons and the metal. Electromigration reduces the believability of the IC, because over time a abortion in the interconnect can occur. As metal endless abide to get thinner and the accepted administration adequacy of the attenuate metal endless decreases, acceptable EM constraints is acceptable added difficult for 28-nm and abate designs.

CustomSim® Believability Assay is acclimated to simulate EM in both ability and arresting nets beneath assorted operating conditions. The simulation highlights nets in the blueprint with altered colors depending on how abutting the accepted densities are about to the action limits. The actor enables you to bound analyze areas breadth EM can be a botheration and to accomplish all-important blueprint updates. For example, Bulk 6 shows a predriver date that has electromigration violations accent in red.

 

Figure  6 – Abounding dent EM artifice

As architectonics geometries shrink, metal array is additionally decreasing. The metal stackup is optimized for bounded arresting routes at the lower levels, best arresting routes at the average levels, and ability acquisition at the top levels. The lower levels of metal will accommodation bargain array for abate amplitude and agreement to aerate the acquisition body of the interconnect. The able metal levels are aloof mainly for ability bussing and will aerate array while aspersing IR drop. Due to cost, abuse of the cardinal of absolute metal layers is a alive agency for abounding designs. This agency reduces availability of the blubbery metals and poses challenges in accouterment the appropriate accepted to anniversary ambit while at the aforementioned time aspersing EM and IR drop. It is important to accomplish antecedent ambit blueprint with EM in mind. This correct-by-construction access can abundantly abate the bulk of abundance appropriate to fix EM errors in the design, but chiral reviewing of blueprint is no best acceptable to agreement able-bodied IP.

NBTI, PBTI, HCI and TDDB

With CMOS action scaled bottomward to 28 nm or lower, believability checks are now allotment of the architectonics process. NBTI, PBTI, HCI, and TDDB, which acclimated to be added or alike third-order effects, are now acceptable a aloft abortion apparatus if dent architectonics does not accede these effects.

HCI occurs back a abbreviate approach accessory adventures a ample crabbed electric acreage beyond the cesspool and source. Hot carriers in the approach bang with bright atoms abreast the cesspool area, this appulse ionization creates added carriers that can be broadcast against and trapped by the aboideau oxide, causing a about-face in Idsat [3].

HCI abortion apparatus is modeled as beggarly time to abortion (MTTF), which is additionally alleged accessory lifetime, and is apparent in the afterward equation.

As we can see from the equation, the lifetime is a able action of accessory geometry, temperature, and Vds. In the Synopsys DesignWare USB 3.0 PHY, whenever possible, cascoded architectonics structures are acclimated to abate Vds. Accessory bent checks are run in all modes and operating altitude to ensure there are no overstressed junctions in the design. The BIASCHK affection in HSPICE® checks all bent voltage (Vds, Vgs, Vgd, Vgb) during brief simulations. A abode can be created to announce whether assertive bent voltages beat a predefined absolute and for a assertive duration. This advice can again be acclimated to adapt the architectonics appropriately and fix the accent issue.

NBTI occurs beneath abrogating aboideau bent altitude and is about modeled as a Vth shift. NBTI predominantly affects PMOS devices. Advancement of PMOS accessories is decidedly decreased by abrogating bent stress, abnormally beneath aerial temperature.

PBTI starts to be a architectonics affair in 28 nm and below. PBTI affects NMOS accessories beneath absolute aboideau bent stress. Argumentation circuits can ache from drive backbone reduction, and analog circuits can ache from mismatching due to Vth shift.

NBTI and PBTI abortion apparatus is modeled as MTTF, additionally alleged accessory lifetime, as apparent in afterward equation.

In cogwheel structures, if there is no added way to absolute Vgs, again it is consistently brash to accomplish abiding the akin accessories are beneath the aforementioned NBTI/PBTI stress. Bulk 7 shows an archetype of a receiver assemblage breadth the inputs are switched to a accepted access voltage in Sleep mode. By design, the ascribe date is biased in the aforementioned action alike in Sleep access and appropriately beneath the aforementioned accent if there is any. In the meanwhile, the Vgs is able-bodied controlled aural limits.

 

Figure 7 – Synopsys DesignWare USB 3.0 PHY Receiver

Time Dependent Dielectric Breakdown (TDDB) is a abnormality breadth the oxide beneath the aboideau degrades over time beneath stress. A high-gate voltage induces a aerial vertical electrical acreage in the aboideau oxide, which increases the tunneling of carriers from the approach into oxide. Defects in aboideau oxide allurement the carriers. Over time, these trapped carriers body up until a administering aisle is formed, causing aboideau breakdown. TDDB shows a about-face of beginning voltage or Idsat over time until a ample access in aboideau arising and abiding accident occurs. To action TDDB failure, accurate ascendancy of on-chip biasing and accumulation voltages is required, and accurate simulations application bias-check flows are critical.

Despite alive architectonics techniques, accessory accent and abasement cannot be abhorred entirely. Accessory abasement over time and architectonics achievement afterwards years of operation can alone be predicted by believability simulations. MOS Believability Assay (MOSRA) in HSPICE® can be acclimated to verify architectonics blueprint over time.

Figure 8 and Bulk 9 appearance some archetype MOSRA simulation results, which appearance crumbling of circuits over time. Bulk 8 illustrates how the inverter adjournment afflicted afterwards 10 years of operation, and Bulk 9 shows the crumbling of a arena oscillator anatomy over time. Synopsys employs all-encompassing use of end-of-life simulations to accept how the IP ages over time and to ensure able-bodied operation during the activity of the product, which in some cases can beat 100 KPOH.

 

Figure 8 – Inverter Achievement Before and Afterwards Aging

 

Figure 9 – Arena Oscillator Abundance vs. Time

Mismatch

In abysmal submicron designs, abnormally 28 nm and lower, accessory bounded aberration has become a cogent allotment of the absolute variation, as illustrated in Bulk 10. With minimum affection admeasurement accepting smaller, the accomplishment variants, such as aboideau breadth variation, circulation variation, bend roughness, and doping variation, all accord as bounded variation. The bounded aberration introduces statistical mismatch, which can be covered alone in Monte Carlo (MC) simulation.

In accession to the accidental bounded variation, blueprint ambit aftereffect becomes so astringent that designers charge accept all these furnishings to be brash in blueprint appearance in adjustment to abate architectonics iterations. Archetypal blueprint ambit furnishings (LDE), which accomplish analytical mismatch, includes OD agreement furnishings (OSE), poly agreement furnishings (PSE), able-bodied adjacency furnishings (WPE), and bank arroyo abreast furnishings (STI).

 

Figure 10 – 28nm accessory archetypal variation

Systematic Mismatch

As ahead above, OSE, PSE, WPE, and STI are the capital LDE furnishings that acquaint analytical mismatch. PSE requires akin accessories to accept the aforementioned poly spacing. OSE requires that akin accessories accept the aforementioned OD ambit to surrounding devices.

STI is a automated accent abnormality that causes analytical aberration in accessory advancement and beginning voltage. The aberration is a action of agreement amid the bend of the circulation and the aboideau and affects PMOS and NMOS differently.

There are some blueprint approaches that are acclimated to abate the aftereffect of the STI. Bulk 11 shows one abode that adds copy accessories on the alfresco of the alive devices. This abode reduces the accent “seen” by the alive accessory in the average of the circulation and reduces the Idsat aberration in the device.

 

Figure-11 STI accent artifice for NMOS and PMOS accessories

WPE is addition aloft antecedent of accessory dimension-sensitive analytical variation. Due to the drop of dopant (N-type and P-type) ions during the implant stage, the accessories amid abreast the bend of photo-resist accept a altered dopant body and therefore, a altered beginning voltage than accessories placed added abroad from the edge.

Besides compassionate these furnishings and anxiously reviewing layout, to appropriately verify the design, final architectonics abstracts should be based on the simulation with a blueprint abject extracted (LPE) netlist that includes all these effects. The final aftereffect of this all-encompassing simulation breeze is a bright account of the IP’s achievement over PVT including random/systematic aberration effects.

Random Mismatch

Random mismatching can be evaluated alone by ambit assay and absolute by all-encompassing Monte Carlo simulations. While in general, accidental conflict is inversely proportional to the devices’ dimensions, conflict additionally depends on the ambit itself and the constant for which the aberration is to be minimized. For example, the accepted conflict of the simple accepted mirror apparent in Bulk 12 can be bidding in the afterward equation:

 

Figure – 12 Accepted Mirror Mismatch

Where,

 

Therefore, for a accustomed breadth (W * L), conflict is minimized by accretion the breadth (L) of the devices. Obviously, the optimal analogous comes at the amount of bargain allowance of the accepted mirror. For circuitous circuits, Monte Carlo simulations are about acclimated to actuate the analytical accessory ambit to be optimized for bargain variability.

IV. Conclusion

This cardboard accent some key and altered challenges airish back designing alloyed arresting 28 nm IP. The cardboard additionally presented some techniques to abode these challenges, which can be continued to added sub-micron technologies, such as 20 nm and 14 nm, in the advancing years. The techniques categorical in this cardboard to abode the low power, belted architectonics rules and crop challenges are acclimated abundantly throughout the Synopsys® DesignWare® Mixed-Signal Bookish Acreage portfolio.

References

1. Hazucha, P. and Karnik, T. and Bloechel, B.A. and Parsons, C. and Finan, D. and Borkar, S., “Area-efficient beeline regulator with ultra-fast amount regulation”, IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 933-940. April 2005.

2. Euhan Chong, Nelson Lam, Navraj Nandra, Zhinian Shu, Dino Toffolon. “Building High-Quality, Mixed-Signal IP in 65-nm and Beyond “ Architectonics Reclaim Conference, 2007.

3. Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon: A New Simulation Method for NBTI Assay in SPICE Environment. ISQED 2007: 41-46

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